# This is a BitKeeper generated patch for the following project:
# Project Name: Linux kernel tree
# This patch format is intended for GNU patch command version 2.5 or higher.
# This patch includes the following deltas:
# ChangeSet 1.1003.1.73+1.1003.9.28 -> 1.1003.31.1
# drivers/char/drm/drm_agpsupport.h 1.10.1.4 -> 1.14
# include/linux/sysctl.h 1.23.1.4 -> 1.27
# kernel/sysctl.c 1.19.1.3 -> 1.22
# Makefile 1.190.1.34 -> 1.193.1.21
# drivers/char/agp/agpgart_be.c 1.41.1.12 -> 1.41.1.13
# arch/i386/kernel/Makefile 1.6.1.1 -> 1.8
# drivers/char/Config.in 1.36.1.11 -> 1.39.1.7
# include/linux/fs.h 1.69.1.13 -> 1.74
# drivers/char/serial.c 1.37 -> 1.38
# arch/i386/kernel/mpparse.c 1.27.1.1 -> 1.29
# drivers/acpi/executer/exfldio.c 1.19.1.1 -> 1.21
# arch/i386/kernel/io_apic.c 1.27.1.1 -> 1.29
# drivers/char/agp/agp.h 1.18.1.2 -> 1.23
# arch/i386/kernel/setup.c 1.68.1.1 -> 1.70
# mm/mremap.c 1.5.1.1 -> 1.7
# fs/Makefile 1.16.1.2 -> 1.19
# fs/Config.in 1.20.1.5 -> 1.24
# include/asm-i386/io_apic.h 1.10.1.1 -> 1.12
# include/linux/highmem.h 1.10.1.2 -> 1.12.1.1
# include/linux/agp_backend.h 1.13.1.3 -> 1.18
# drivers/acpi/Config.in 1.9.1.1 -> 1.11
# Documentation/Configure.help 1.164 -> 1.165
# drivers/char/Makefile 1.27.1.7 -> 1.31.1.3
# fs/inode.c 1.36.1.2 -> 1.39
# arch/i386/kernel/pci-irq.c 1.20.1.1 -> 1.22
#
diff -Nru a/Documentation/Configure.help b/Documentation/Configure.help
--- a/Documentation/Configure.help Wed Oct 8 09:05:48 2003
+++ b/Documentation/Configure.help Wed Oct 8 09:05:48 2003
@@ -12,8 +12,8 @@
# <http://nevod.perm.su/service/linux/doc/kernel/Configure.help>
# - French, by Pierre Tane <mailto:tanep@bigfoot.com>, at
# <http://www.traduc.org/kernelfr/>
-# - Polish, by Dominik Mierzejewski <mailto:dmierzej@elka.pw.edu.pl>, at
-# <http://home.elka.pw.edu.pl/~dmierzej/linux/kernel/>
+# - Polish, by Dominik Mierzejewski <mailto:dominik@piorunek.pl>, at
+# <http://www.piorunek.pl/~dominik/linux/kernel/>
# - German, by SuSE, at <http://www.suse.de/~ke/kernel/>. This patch
# also includes infrastructure to support different languages.
# - Catalan, by Antoni Bella <mailto:bella5@teleline.es>, at
@@ -12886,10 +12886,18 @@
If you say Y here, you will be able to set per user limits for disk
usage (also called disk quotas). Currently, it works only for the
ext2 file system. You need additional software in order to use quota
- support; for details, read the Quota mini-HOWTO, available from
+ support (you can download sources from
+ <http://www.sf.net/projects/linuxquota/>). For further details, read
+ the Quota mini-HOWTO, available from
<http://www.tldp.org/docs.html#howto>. Probably the quota
support is only useful for multi user systems. If unsure, say N.
+VFS v0 quota format support
+CONFIG_QFMT_V2
+ This quota format allows using quotas with 32-bit UIDs/GIDs. If you
+ need this functionality say Y here. Note that you will need latest
+ quota utilities for new quota format with this kernel.
+
Memory Technology Device (MTD) support
CONFIG_MTD
Memory Technology Devices are flash, RAM and similar chips, often
@@ -16086,7 +16094,7 @@
say M here and read <file:Documentation/modules.txt>. If unsure,
say N.
-Apple Macintosh file system support
+Apple HFS file system support
CONFIG_HFS_FS
If you say Y here, you will be able to mount Macintosh-formatted
floppy disks and hard drive partitions with full read-write access.
@@ -16098,6 +16106,21 @@
whenever you want). The module is called hfs.o. If you want to
compile it as a module, say M here and read
<file:Documentation/modules.txt>.
+
+Apple HFS+ (Extended HFS) file system support
+CONFIG_HFSPLUS_FS
+ If you say Y here, you will be able to mount extended format
+ Macintosh-formatted hard drive partitions with full read-write access.
+
+ This file system is often called HFS+ and was introduced with
+ MacOS 8. It includes all Mac specific filesystem data such as
+ data forks and creator codes, but it also has several UNIX
+ style features such as file ownership and permissions.
+
+ This file system is also available as a module ( = code which can
+ be inserted in and removed from the running kernel whenever you
+ want). The module is called hfsplus.o. If you want to compile it
+ as a module, say M here and read Documentation/modules.txt.
ROM file system support
CONFIG_ROMFS_FS
diff -Nru a/Makefile b/Makefile
--- a/Makefile Wed Oct 8 09:05:47 2003
+++ b/Makefile Wed Oct 8 09:05:47 2003
@@ -93,6 +93,7 @@
CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
-fno-strict-aliasing -fno-common
+CFLAGS += -g
ifndef CONFIG_FRAME_POINTER
CFLAGS += -fomit-frame-pointer
endif
@@ -304,8 +305,7 @@
$(CONFIG_SHELL) scripts/Configure -d arch/$(ARCH)/config.in
xconfig: symlinks
- $(MAKE) -C scripts kconfig.tk
- wish -f scripts/kconfig.tk
+ @echo -e "***\n* Sorry, xconfig is broken; use \"make menuconfig\" instead.\n***"
menuconfig: include/linux/version.h symlinks
$(MAKE) -C scripts/lxdialog all
diff -Nru a/drivers/char/Config.in b/drivers/char/Config.in
--- a/drivers/char/Config.in Wed Oct 8 09:05:47 2003
+++ b/drivers/char/Config.in Wed Oct 8 09:05:47 2003
@@ -24,6 +24,9 @@
tristate ' Atomwide serial port support' CONFIG_ATOMWIDE_SERIAL
tristate ' Dual serial port support' CONFIG_DUALSP_SERIAL
fi
+ if [ "$CONFIG_ACPI" = "y" ]; then
+ bool ' Support for serial ports defined in ACPI namespace' CONFIG_SERIAL_ACPI
+ fi
fi
dep_mbool 'Extended dumb serial driver options' CONFIG_SERIAL_EXTENDED $CONFIG_SERIAL
if [ "$CONFIG_SERIAL_EXTENDED" = "y" ]; then
@@ -313,6 +316,7 @@
bool ' NVIDIA chipset support' CONFIG_AGP_NVIDIA
fi
if [ "$CONFIG_IA64" = "y" ]; then
+ bool ' Intel 460GX support' CONFIG_AGP_I460
bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
fi
fi
diff -Nru a/drivers/char/Makefile b/drivers/char/Makefile
--- a/drivers/char/Makefile Wed Oct 8 09:05:48 2003
+++ b/drivers/char/Makefile Wed Oct 8 09:05:48 2003
@@ -182,6 +182,7 @@
obj-$(CONFIG_HIL) += hp_keyb.o
obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o
+obj-$(CONFIG_HP_SIMSERIAL) += simserial.o
obj-$(CONFIG_ROCKETPORT) += rocket.o
obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
diff -Nru a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
--- a/drivers/char/agp/agp.h Wed Oct 8 09:05:47 2003
+++ b/drivers/char/agp/agp.h Wed Oct 8 09:05:47 2003
@@ -250,6 +250,9 @@
#ifndef PCI_DEVICE_ID_INTEL_82443GX_1
#define PCI_DEVICE_ID_INTEL_82443GX_1 0x71a1
#endif
+#ifndef PCI_DEVICE_ID_INTEL_460GX
+#define PCI_DEVICE_ID_INTEL_460GX 0x84ea
+#endif
#ifndef PCI_DEVICE_ID_AMD_IRONGATE_0
#define PCI_DEVICE_ID_AMD_IRONGATE_0 0x7006
#endif
@@ -301,6 +304,14 @@
#define INTEL_NBXCFG 0x50
#define INTEL_ERRSTS 0x91
+/* Intel 460GX Registers */
+#define INTEL_I460_APBASE 0x10
+#define INTEL_I460_BAPBASE 0x98
+#define INTEL_I460_GXBCTL 0xa0
+#define INTEL_I460_AGPSIZ 0xa2
+#define INTEL_I460_ATTBASE 0xfe200000
+#define INTEL_I460_GATT_VALID (1UL << 24)
+#define INTEL_I460_GATT_COHERENT (1UL << 25)
/* Intel 855GM/852GM registers */
#define I855_GMCH_CTRL 0x52
#define I855_GMCH_ENABLED 0x4
@@ -466,13 +477,15 @@
#define NVIDIA_3_APBASE 0x50
#define NVIDIA_3_APLIMIT 0x54
-/* HP ZX1 SBA registers */
-#define HP_ZX1_CTRL 0x200
+/* HP ZX1 IOC registers */
#define HP_ZX1_IBASE 0x300
#define HP_ZX1_IMASK 0x308
#define HP_ZX1_PCOM 0x310
#define HP_ZX1_TCNFG 0x318
#define HP_ZX1_PDIR_BASE 0x320
-#define HP_ZX1_CACHE_FLUSH 0x428
+
+/* HP ZX1 LBA registers */
+#define HP_ZX1_AGP_STATUS 0x64
+#define HP_ZX1_AGP_COMMAND 0x68
#endif /* _AGP_BACKEND_PRIV_H */
diff -Nru a/drivers/char/agp/agpgart_be.c b/drivers/char/agp/agpgart_be.c
--- a/drivers/char/agp/agpgart_be.c Wed Oct 8 09:05:47 2003
+++ b/drivers/char/agp/agpgart_be.c Wed Oct 8 09:05:47 2003
@@ -23,6 +23,12 @@
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
+
+/*
+ * Intel(R) 855GM/852GM and 865G support, added by
+ * David Dawes <dawes@tungstengraphics.com>.
+ */
+
#include <linux/config.h>
#include <linux/version.h>
#include <linux/module.h>
@@ -47,6 +53,9 @@
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
#include <asm/smplock.h>
+#ifdef CONFIG_AGP_NVIDIA
+ #include <asm/msr.h>
+#endif
#include <linux/agp_backend.h>
#include "agp.h"
@@ -643,7 +652,7 @@
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
SetPageReserved(page);
- agp_bridge.gatt_table_real = (unsigned long *) table;
+ agp_bridge.gatt_table_real = (u32 *) table;
agp_gatt_table = (void *)table;
#ifdef CONFIG_X86
err = change_page_attr(virt_to_page(table), 1<<page_order, PAGE_KERNEL_NOCACHE);
@@ -1178,34 +1187,64 @@
u16 gmch_ctrl;
int gtt_entries;
u8 rdct;
+ int local = 0;
static const int ddt[4] = { 0, 16, 32, 64 };
pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
- switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
- case I830_GMCH_GMS_STOLEN_512:
- gtt_entries = KB(512) - KB(132);
- printk(KERN_INFO PFX "detected %dK stolen memory.\n",gtt_entries / KB(1));
- break;
- case I830_GMCH_GMS_STOLEN_1024:
- gtt_entries = MB(1) - KB(132);
- printk(KERN_INFO PFX "detected %dK stolen memory.\n",gtt_entries / KB(1));
- break;
- case I830_GMCH_GMS_STOLEN_8192:
- gtt_entries = MB(8) - KB(132);
- printk(KERN_INFO PFX "detected %dK stolen memory.\n",gtt_entries / KB(1));
- break;
- case I830_GMCH_GMS_LOCAL:
- rdct = INREG8(intel_i830_private.registers,I830_RDRAM_CHANNEL_TYPE);
- gtt_entries = (I830_RDRAM_ND(rdct) + 1) * MB(ddt[I830_RDRAM_DDT(rdct)]);
- printk(KERN_INFO PFX "detected %dK local memory.\n",gtt_entries / KB(1));
- break;
- default:
- printk(KERN_INFO PFX "no video memory detected.\n");
- gtt_entries = 0;
- break;
+ if (agp_bridge.dev->device != PCI_DEVICE_ID_INTEL_830_M_0 &&
+ agp_bridge.dev->device != PCI_DEVICE_ID_INTEL_845_G_0) {
+ switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
+ case I855_GMCH_GMS_STOLEN_1M:
+ gtt_entries = MB(1) - KB(132);
+ break;
+ case I855_GMCH_GMS_STOLEN_4M:
+ gtt_entries = MB(4) - KB(132);
+ break;
+ case I855_GMCH_GMS_STOLEN_8M:
+ gtt_entries = MB(8) - KB(132);
+ break;
+ case I855_GMCH_GMS_STOLEN_16M:
+ gtt_entries = MB(16) - KB(132);
+ break;
+ case I855_GMCH_GMS_STOLEN_32M:
+ gtt_entries = MB(32) - KB(132);
+ break;
+ default:
+ gtt_entries = 0;
+ break;
+ }
+ } else
+ {
+ switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
+ case I830_GMCH_GMS_STOLEN_512:
+ gtt_entries = KB(512) - KB(132);
+ break;
+ case I830_GMCH_GMS_STOLEN_1024:
+ gtt_entries = MB(1) - KB(132);
+ break;
+ case I830_GMCH_GMS_STOLEN_8192:
+ gtt_entries = MB(8) - KB(132);
+ break;
+ case I830_GMCH_GMS_LOCAL:
+ rdct = INREG8(intel_i830_private.registers,
+ I830_RDRAM_CHANNEL_TYPE);
+ gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
+ MB(ddt[I830_RDRAM_DDT(rdct)]);
+ local = 1;
+ break;
+ default:
+ gtt_entries = 0;
+ break;
+ }
}
+ if (gtt_entries > 0)
+ printk(KERN_INFO PFX "Detected %dK %s memory.\n",
+ gtt_entries / KB(1), local ? "local" : "stolen");
+ else
+ printk(KERN_INFO PFX
+ "No pre-allocated video memory detected.\n");
gtt_entries /= KB(4);
intel_i830_private.gtt_entries = gtt_entries;
@@ -1258,9 +1297,16 @@
u16 gmch_ctrl;
aper_size_info_fixed *values;
- pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
values = A_SIZE_FIX(agp_bridge.aperture_sizes);
+ if (agp_bridge.dev->device != PCI_DEVICE_ID_INTEL_830_M_0 &&
+ agp_bridge.dev->device != PCI_DEVICE_ID_INTEL_845_G_0) {
+ agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
+ agp_bridge.aperture_size_idx = 0;
+ return(values[0].size);
+ }
+
+ pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
agp_bridge.aperture_size_idx = 0;
@@ -3112,8 +3158,8 @@
return retval;
}
- agp_bridge.gatt_table_real = page_dir.real;
- agp_bridge.gatt_table = page_dir.remapped;
+ agp_bridge.gatt_table_real = (u32 *)page_dir.real;
+ agp_bridge.gatt_table = (u32 *)page_dir.remapped;
agp_bridge.gatt_bus_addr = virt_to_bus(page_dir.real);
/* Get the address for the gart region.
@@ -3139,8 +3185,8 @@
{
amd_page_map page_dir;
- page_dir.real = agp_bridge.gatt_table_real;
- page_dir.remapped = agp_bridge.gatt_table;
+ page_dir.real = (unsigned long *)agp_bridge.gatt_table_real;
+ page_dir.remapped = (unsigned long *)agp_bridge.gatt_table;
amd_free_gatt_pages();
amd_free_page_map(&page_dir);
@@ -4157,8 +4203,8 @@
return retval;
}
- agp_bridge.gatt_table_real = page_dir.real;
- agp_bridge.gatt_table = page_dir.remapped;
+ agp_bridge.gatt_table_real = (u32 *)page_dir.real;
+ agp_bridge.gatt_table = (u32 *)page_dir.remapped;
agp_bridge.gatt_bus_addr = virt_to_bus(page_dir.real);
/* Get the address for the gart region.
@@ -4186,8 +4232,8 @@
{
serverworks_page_map page_dir;
- page_dir.real = agp_bridge.gatt_table_real;
- page_dir.remapped = agp_bridge.gatt_table;
+ page_dir.real = (unsigned long *)agp_bridge.gatt_table_real;
+ page_dir.remapped = (unsigned long *)agp_bridge.gatt_table;
serverworks_free_gatt_pages();
serverworks_free_page_map(&page_dir);
@@ -4520,6 +4566,330 @@
#endif /* CONFIG_AGP_SWORKS */
+#ifdef CONFIG_AGP_NVIDIA
+
+static struct _nvidia_private {
+ struct pci_dev *dev_1;
+ struct pci_dev *dev_2;
+ struct pci_dev *dev_3;
+ volatile u32 *aperture;
+ int num_active_entries;
+ off_t pg_offset;
+} nvidia_private;
+
+static int nvidia_fetch_size(void)
+{
+ int i;
+ u8 size_value;
+ aper_size_info_8 *values;
+
+ pci_read_config_byte(agp_bridge.dev, NVIDIA_0_APSIZE, &size_value);
+ size_value &= 0x0f;
+ values = A_SIZE_8(agp_bridge.aperture_sizes);
+
+ for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ if (size_value == values[i].size_value) {
+ agp_bridge.previous_size =
+ agp_bridge.current_size = (void *) (values + i);
+ agp_bridge.aperture_size_idx = i;
+ return values[i].size;
+ }
+ }
+
+ return 0;
+}
+
+#define SYSCFG 0xC0010010
+#define IORR_BASE0 0xC0010016
+#define IORR_MASK0 0xC0010017
+#define AMD_K7_NUM_IORR 2
+
+static int nvidia_init_iorr(u32 base, u32 size)
+{
+ u32 base_hi, base_lo;
+ u32 mask_hi, mask_lo;
+ u32 sys_hi, sys_lo;
+ u32 iorr_addr, free_iorr_addr;
+
+ /* Find the iorr that is already used for the base */
+ /* If not found, determine the uppermost available iorr */
+ free_iorr_addr = AMD_K7_NUM_IORR;
+ for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
+ rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
+ rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
+
+ if ((base_lo & 0xfffff000) == (base & 0xfffff000))
+ break;
+
+ if ((mask_lo & 0x00000800) == 0)
+ free_iorr_addr = iorr_addr;
+ }
+
+ if (iorr_addr >= AMD_K7_NUM_IORR) {
+ iorr_addr = free_iorr_addr;
+ if (iorr_addr >= AMD_K7_NUM_IORR)
+ return -EINVAL;
+ }
+
+ base_hi = 0x0;
+ base_lo = (base & ~0xfff) | 0x18;
+ mask_hi = 0xf;
+ mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800;
+ wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
+ wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
+
+ rdmsr(SYSCFG, sys_lo, sys_hi);
+ sys_lo |= 0x00100000;
+ wrmsr(SYSCFG, sys_lo, sys_hi);
+
+ return 0;
+}
+
+static int nvidia_configure(void)
+{
+ int i, rc, num_dirs;
+ u32 apbase, aplimit;
+ aper_size_info_8 *current_size;
+ u32 temp;
+
+ current_size = A_SIZE_8(agp_bridge.current_size);
+
+ /* aperture size */
+ pci_write_config_byte(agp_bridge.dev, NVIDIA_0_APSIZE,
+ current_size->size_value);
+
+ /* address to map to */
+ pci_read_config_dword(agp_bridge.dev, NVIDIA_0_APBASE, &apbase);
+ apbase &= PCI_BASE_ADDRESS_MEM_MASK;
+ agp_bridge.gart_bus_addr = apbase;
+ aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
+ pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
+ pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);
+ pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);
+ pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);
+ if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024)))
+ return rc;
+
+ /* directory size is 64k */
+ num_dirs = current_size->size / 64;
+ nvidia_private.num_active_entries = current_size->num_entries;
+ nvidia_private.pg_offset = 0;
+ if (num_dirs == 0) {
+ num_dirs = 1;
+ nvidia_private.num_active_entries /= (64 / current_size->size);
+ nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
+ ~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;
+ }
+
+ /* attbase */
+ for(i = 0; i < 8; i++) {
+ pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
+ (agp_bridge.gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
+ }
+
+ /* gtlb control */
+ pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
+ pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL,
+ temp | 0x11);
+
+ /* gart control */
+ pci_read_config_dword(agp_bridge.dev, NVIDIA_0_APSIZE, &temp);
+ pci_write_config_dword(agp_bridge.dev, NVIDIA_0_APSIZE,
+ temp | 0x100);
+
+ /* map aperture */
+ nvidia_private.aperture =
+ (volatile u32 *) ioremap(apbase, 33 * PAGE_SIZE);
+
+ return 0;
+}
+
+static void nvidia_cleanup(void)
+{
+ aper_size_info_8 *previous_size;
+ u32 temp;
+
+ /* gart control */
+ pci_read_config_dword(agp_bridge.dev, NVIDIA_0_APSIZE, &temp);
+ pci_write_config_dword(agp_bridge.dev, NVIDIA_0_APSIZE,
+ temp & ~(0x100));
+
+ /* gtlb control */
+ pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
+ pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL,
+ temp & ~(0x11));
+
+ /* unmap aperture */
+ iounmap((void *) nvidia_private.aperture);
+
+ /* restore previous aperture size */
+ previous_size = A_SIZE_8(agp_bridge.previous_size);
+ pci_write_config_byte(agp_bridge.dev, NVIDIA_0_APSIZE,
+ previous_size->size_value);
+
+ /* restore iorr for previous aperture size */
+ nvidia_init_iorr(agp_bridge.gart_bus_addr,
+ previous_size->size * 1024 * 1024);
+}
+
+static void nvidia_tlbflush(agp_memory * mem)
+{
+ int i;
+ unsigned long end;
+ u32 wbc_reg, wbc_mask, temp;
+
+ /* flush chipset */
+ switch(agp_bridge.type) {
+ case NVIDIA_NFORCE:
+ wbc_mask = 0x00010000;
+ break;
+ case NVIDIA_NFORCE2:
+ wbc_mask = 0x80000000;
+ break;
+ default:
+ wbc_mask = 0;
+ break;
+ }
+
+ if (wbc_mask) {
+ pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
+ wbc_reg |= wbc_mask;
+ pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg);
+
+ end = jiffies + 3*HZ;
+ do {
+ pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
+ if ((signed)(end - jiffies) <= 0) {
+ printk(KERN_ERR "TLB flush took more than 3 seconds.\n");
+ }
+ } while (wbc_reg & wbc_mask);
+ }
+
+ /* flush TLB entries */
+ for(i = 0; i < 32 + 1; i++)
+ temp = nvidia_private.aperture[i * PAGE_SIZE / sizeof(u32)];
+ for(i = 0; i < 32 + 1; i++)
+ temp = nvidia_private.aperture[i * PAGE_SIZE / sizeof(u32)];
+}
+
+static unsigned long nvidia_mask_memory(unsigned long addr, int type)
+{
+ /* Memory type is ignored */
+
+ return addr | agp_bridge.masks[0].mask;
+}
+
+static int nvidia_insert_memory(agp_memory * mem,
+ off_t pg_start, int type)
+{
+ int i, j;
+
+ if ((type != 0) || (mem->type != 0))
+ return -EINVAL;
+
+ if ((pg_start + mem->page_count) >
+ (nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
+ return -EINVAL;
+
+ for(j = pg_start; j < (pg_start + mem->page_count); j++) {
+ if (!PGE_EMPTY(agp_bridge.gatt_table[nvidia_private.pg_offset + j])) {
+ return -EBUSY;
+ }
+ }
+
+ if (mem->is_flushed == FALSE) {
+ CACHE_FLUSH();
+ mem->is_flushed = TRUE;
+ }
+ for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
+ agp_bridge.gatt_table[nvidia_private.pg_offset + j] = agp_bridge.mask_memory(mem->memory[i], mem->type);
+ }
+
+ agp_bridge.tlb_flush(mem);
+ return 0;
+}
+
+static int nvidia_remove_memory(agp_memory * mem, off_t pg_start,
+ int type)
+{
+ int i;
+
+ if ((type != 0) || (mem->type != 0))
+ return -EINVAL;
+
+ for (i = pg_start; i < (mem->page_count + pg_start); i++) {
+ agp_bridge.gatt_table[nvidia_private.pg_offset + i] =
+ (unsigned long) agp_bridge.scratch_page;
+ }
+
+ agp_bridge.tlb_flush(mem);
+ return 0;
+}
+
+static aper_size_info_8 nvidia_generic_sizes[5] =
+{
+ {512, 131072, 7, 0},
+ {256, 65536, 6, 8},
+ {128, 32768, 5, 12},
+ {64, 16384, 4, 14},
+ /* The 32M mode still requires a 64k gatt */
+ {32, 16384, 4, 15}
+};
+
+static gatt_mask nvidia_generic_masks[] =
+{
+ {0x00000001, 0}
+};
+
+static int __init nvidia_generic_setup (struct pci_dev *pdev)
+{
+ nvidia_private.dev_1 =
+ pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1));
+ nvidia_private.dev_2 =
+ pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
+ nvidia_private.dev_3 =
+ pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
+
+ if((nvidia_private.dev_1 == NULL) ||
+ (nvidia_private.dev_2 == NULL) ||
+ (nvidia_private.dev_3 == NULL)) {
+ printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
+ "nForce/nForce2 chipset, but could not find "
+ "the secondary devices.\n");
+ agp_bridge.type = NOT_SUPPORTED;
+ return -ENODEV;
+ }
+
+ agp_bridge.masks = nvidia_generic_masks;
+ agp_bridge.aperture_sizes = (void *) nvidia_generic_sizes;
+ agp_bridge.size_type = U8_APER_SIZE;
+ agp_bridge.num_aperture_sizes = 5;
+ agp_bridge.dev_private_data = (void *) &nvidia_private;
+ agp_bridge.needs_scratch_page = FALSE;
+ agp_bridge.configure = nvidia_configure;
+ agp_bridge.fetch_size = nvidia_fetch_size;
+ agp_bridge.cleanup = nvidia_cleanup;
+ agp_bridge.tlb_flush = nvidia_tlbflush;
+ agp_bridge.mask_memory = nvidia_mask_memory;
+ agp_bridge.agp_enable = agp_generic_agp_enable;
+ agp_bridge.cache_flush = global_cache_flush;
+ agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge.insert_memory = nvidia_insert_memory;
+ agp_bridge.remove_memory = nvidia_remove_memory;
+ agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge.free_by_type = agp_generic_free_by_type;
+ agp_bridge.agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge.agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge.suspend = agp_generic_suspend;
+ agp_bridge.resume = agp_generic_resume;
+ agp_bridge.cant_use_aperture = 0;
+
+ return 0;
+}
+
+#endif /* CONFIG_AGP_NVIDIA */
+
#ifdef CONFIG_AGP_HP_ZX1
#ifndef log2
@@ -5062,15 +5432,38 @@
{ PCI_DEVICE_ID_INTEL_830_M_0,
PCI_VENDOR_ID_INTEL,
INTEL_I830_M,
- "Intel",
- "i830M",
+ "Intel(R)",
+ "830M",
intel_830mp_setup },
- { PCI_DEVICE_ID_INTEL_845_G_0,
+
+ { PCI_DEVICE_ID_INTEL_845_G_0,
PCI_VENDOR_ID_INTEL,
INTEL_I845_G,
- "Intel",
- "i845G",
+ "Intel(R)",
+ "845G",
intel_845_setup },
+
+ { PCI_DEVICE_ID_INTEL_855_GM_0,
+ PCI_VENDOR_ID_INTEL,
+ INTEL_I855_PM,
+ "Intel(R)",
+ "855PM",
+ intel_845_setup },
+
+ { PCI_DEVICE_ID_INTEL_855_PM_0,
+ PCI_VENDOR_ID_INTEL,
+ INTEL_I855_PM,
+ "Intel(R)",
+ "855PM",
+ intel_845_setup },
+
+ { PCI_DEVICE_ID_INTEL_865_G_0,
+ PCI_VENDOR_ID_INTEL,
+ INTEL_I865_G,
+ "Intel(R)",
+ "865G",
+ intel_845_setup },
+
{ PCI_DEVICE_ID_INTEL_840_0,
PCI_VENDOR_ID_INTEL,
INTEL_I840,
@@ -5120,12 +5513,24 @@
"SiS",
"740",
sis_generic_setup },
+ { PCI_DEVICE_ID_SI_651,
+ PCI_VENDOR_ID_SI,
+ SIS_GENERIC,
+ "SiS",
+ "651",
+ sis_generic_setup },
{ PCI_DEVICE_ID_SI_650,
PCI_VENDOR_ID_SI,
SIS_GENERIC,
"SiS",
"650",
sis_generic_setup },
+ { PCI_DEVICE_ID_SI_651,
+ PCI_VENDOR_ID_SI,
+ SIS_GENERIC,
+ "SiS",
+ "651",
+ sis_generic_setup },
{ PCI_DEVICE_ID_SI_645,
PCI_VENDOR_ID_SI,
SIS_GENERIC,
@@ -5138,6 +5543,12 @@
"SiS",
"646",
sis_generic_setup },
+ { PCI_DEVICE_ID_SI_648,
+ PCI_VENDOR_ID_SI,
+ SIS_GENERIC,
+ "SiS",
+ "648",
+ sis_generic_setup },
{ PCI_DEVICE_ID_SI_735,
PCI_VENDOR_ID_SI,
SIS_GENERIC,
@@ -5150,6 +5561,12 @@
"SiS",
"745",
sis_generic_setup },
+ { PCI_DEVICE_ID_SI_746,
+ PCI_VENDOR_ID_SI,
+ SIS_GENERIC,
+ "SiS",
+ "746",
+ sis_generic_setup },
{ PCI_DEVICE_ID_SI_730,
PCI_VENDOR_ID_SI,
SIS_GENERIC,
@@ -5213,6 +5630,12 @@
"Via",
"MVP3",
via_generic_setup },
+ { PCI_DEVICE_ID_VIA_8601_0,
+ PCI_VENDOR_ID_VIA,
+ VIA_APOLLO_PLE133,
+ "Via",
+ "Apollo PLE133",
+ via_generic_setup },
{ PCI_DEVICE_ID_VIA_82C691_0,
PCI_VENDOR_ID_VIA,
VIA_APOLLO_PRO,
@@ -5237,17 +5660,29 @@
"Via",
"Apollo Pro KT266",
via_generic_setup },
+ { PCI_DEVICE_ID_VIA_8375,
+ PCI_VENDOR_ID_VIA,
+ VIA_APOLLO_KM266,
+ "Via",
+ "Apollo Pro KM266 / KL266",
+ via_generic_setup },
+ { PCI_DEVICE_ID_VIA_8377_0,
+ PCI_VENDOR_ID_VIA,
+ VIA_APOLLO_KT400,
+ "Via",
+ "Apollo Pro KT400",
+ via_generic_setup },
{ PCI_DEVICE_ID_VIA_8377_0,
PCI_VENDOR_ID_VIA,
VIA_APOLLO_KT400,
"Via",
"Apollo Pro KT400",
via_generic_setup },
- { PCI_DEVICE_ID_VIA_P4X333,
+ { PCI_DEVICE_ID_VIA_P4M266,
PCI_VENDOR_ID_VIA,
- VIA_APOLLO_P4X400,
+ VIA_APOLLO_P4M266,
"Via",
- "Apollo P4X400",
+ "Apollo P4M266",
via_generic_setup },
{ 0,
PCI_VENDOR_ID_VIA,
@@ -5257,6 +5692,27 @@
via_generic_setup },
#endif /* CONFIG_AGP_VIA */
+#ifdef CONFIG_AGP_NVIDIA
+ { PCI_DEVICE_ID_NVIDIA_NFORCE,
+ PCI_VENDOR_ID_NVIDIA,
+ NVIDIA_NFORCE,
+ "NVIDIA",
+ "nForce",
+ nvidia_generic_setup },
+ { PCI_DEVICE_ID_NVIDIA_NFORCE2,
+ PCI_VENDOR_ID_NVIDIA,
+ NVIDIA_NFORCE2,
+ "NVIDIA",
+ "nForce2",
+ nvidia_generic_setup },
+ { 0,
+ PCI_VENDOR_ID_NVIDIA,
+ NVIDIA_GENERIC,
+ "NVIDIA",
+ "Generic",
+ nvidia_generic_setup },
+#endif /* CONFIG_AGP_NVIDIA */
+
{ 0, }, /* dummy final entry, always present */
};
@@ -5462,10 +5918,14 @@
* with an external graphics
* card. It will be initialized later
*/
+ printk(KERN_ERR PFX "Detected an "
+ "Intel(R) 845G, but could not find the"
+ " secondary device. Assuming a "
+ "non-integrated video card.\n");
agp_bridge.type = INTEL_I845_G;
break;
}
- printk(KERN_INFO PFX "Detected an Intel "
+ printk(KERN_INFO PFX "Detected an Intel(R) "
"845G Chipset.\n");
agp_bridge.type = INTEL_I810;
return intel_i830_setup(i810_dev);
@@ -5487,8 +5947,116 @@
agp_bridge.type = INTEL_I830_M;
break;
}
- printk(KERN_INFO PFX "Detected an Intel "
+ printk(KERN_INFO PFX "Detected an Intel(R) "
"830M Chipset.\n");
+ agp_bridge.type = INTEL_I810;
+ return intel_i830_setup(i810_dev);
+ case PCI_DEVICE_ID_INTEL_855_GM_0:
+ i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_855_GM_1, NULL);
+ if(i810_dev && PCI_FUNC(i810_dev->devfn) != 0) {
+ i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_855_GM_1, i810_dev);
+ }
+ if (i810_dev == NULL) {
+ /*
+ * We probably have an 855PM chipset
+ * with an external graphics
+ * card. It will be initialized later.
+ */
+ agp_bridge.type = INTEL_I855_PM;
+ break;
+ }
+ {
+ u32 capval = 0;
+ const char *name = "855GM/852GM";
+
+ pci_read_config_dword(dev, I85X_CAPID, &capval);
+ switch ((capval >> I85X_VARIANT_SHIFT) &
+ I85X_VARIANT_MASK) {
+ case I855_GME:
+ name = "855GME";
+ break;
+ case I855_GM:
+ name = "855GM";
+ break;
+ case I852_GME:
+ name = "852GME";
+ break;
+ case I852_GM:
+ name = "852GM";
+ break;
+ }
+ printk(KERN_INFO PFX "Detected an Intel(R) "
+ "%s Chipset.\n", name);
+ }
+ agp_bridge.type = INTEL_I810;
+ return intel_i830_setup(i810_dev);
+ case PCI_DEVICE_ID_INTEL_855_PM_0:
+ i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_855_PM_1, NULL);
+ if(i810_dev && PCI_FUNC(i810_dev->devfn) != 0) {
+ i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_855_PM_1, i810_dev);
+ }
+ if (i810_dev == NULL) {
+ /*
+ * We probably have an 855PM chipset
+ * with an external graphics
+ * card. It will be initialized later.
+ */
+ agp_bridge.type = INTEL_I855_PM;
+ break;
+ }
+ {
+ u32 capval = 0;
+ const char *name = "855PM/852PM";
+
+ pci_read_config_dword(dev, I85X_CAPID, &capval);
+ switch ((capval >> I85X_VARIANT_SHIFT) &
+ I85X_VARIANT_MASK) {
+ case I855_PME:
+ name = "855PME";
+ break;
+ case I855_PM:
+ name = "855PM";
+ break;
+ case I852_PME:
+ name = "852PME";
+ break;
+ case I852_PM:
+ name = "852PM";
+ break;
+ }
+ printk(KERN_INFO PFX "Detected an Intel(R) "
+ "%s Chipset.\n", name);
+ }
+ agp_bridge.type = INTEL_I810;
+ return intel_i830_setup(i810_dev);
+ case PCI_DEVICE_ID_INTEL_865_G_0:
+ i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_865_G_1, NULL);
+ if(i810_dev && PCI_FUNC(i810_dev->devfn) != 0) {
+ i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_865_G_1, i810_dev);
+ }
+
+ if (i810_dev == NULL) {
+ /*
+ * We probably have a 865G chipset
+ * with an external graphics
+ * card. It will be initialized later
+ */
+ printk(KERN_ERR PFX "Detected an "
+ "Intel(R) 865G, but could not"
+ " find the"
+ " secondary device. Assuming a "
+ "non-integrated video card.\n");
+ agp_bridge.type = INTEL_I865_G;
+ break;
+ }
+ printk(KERN_INFO PFX "Detected an Intel(R) "
+ "865G Chipset.\n");
agp_bridge.type = INTEL_I810;
return intel_i830_setup(i810_dev);
default:
diff -Nru a/drivers/char/drm/drm_agpsupport.h b/drivers/char/drm/drm_agpsupport.h
--- a/drivers/char/drm/drm_agpsupport.h Wed Oct 8 09:05:47 2003
+++ b/drivers/char/drm/drm_agpsupport.h Wed Oct 8 09:05:47 2003
@@ -270,6 +270,7 @@
case INTEL_I840: head->chipset = "Intel i840"; break;
case INTEL_I845: head->chipset = "Intel i845"; break;
case INTEL_I850: head->chipset = "Intel i850"; break;
+ case INTEL_460GX: head->chipset = "Intel 460GX"; break;
case VIA_GENERIC: head->chipset = "VIA"; break;
case VIA_VP3: head->chipset = "VIA VP3"; break;
diff -Nru a/drivers/char/serial.c b/drivers/char/serial.c
--- a/drivers/char/serial.c Wed Oct 8 09:05:47 2003
+++ b/drivers/char/serial.c Wed Oct 8 09:05:47 2003
@@ -4432,9 +4432,10 @@
#ifdef CONFIG_DDB5074
pbn_nec_nile4,
#endif
-#if 0
+
+ pbn_dci_pccom4,
pbn_dci_pccom8,
-#endif
+
pbn_xircom_combo,
pbn_siig10x_0,
@@ -4528,9 +4529,10 @@
{ SPCI_FL_BASE0, 1, 520833, /* pbn_nec_nile4 */
64, 3, NULL, 0x300 },
#endif
-#if 0 /* PCI_DEVICE_ID_DCI_PCCOM8 ? */ /* pbn_dci_pccom8 */
- { SPCI_FL_BASE3, 8, 115200, 8 },
-#endif
+
+ {SPCI_FL_BASE3, 4, 115200, 8}, /* pbn_dci_pccom4 */
+ {SPCI_FL_BASE3, 8, 115200, 8}, /* pbn_dci_pccom8 */
+
{ SPCI_FL_BASE0, 1, 115200, /* pbn_xircom_combo */
0, 0, pci_xircom_fn },
@@ -5062,11 +5064,12 @@
pbn_nec_nile4 },
#endif
-#if 0 /* PCI_DEVICE_ID_DCI_PCCOM8 ? */
+ { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_dci_pccom4 },
{ PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_dci_pccom8 },
-#endif
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, },
diff -Nru a/fs/Config.in b/fs/Config.in
--- a/fs/Config.in Wed Oct 8 09:05:48 2003
+++ b/fs/Config.in Wed Oct 8 09:05:48 2003
@@ -54,6 +54,10 @@
bool 'Virtual memory file system support (former shm fs)' CONFIG_TMPFS
define_bool CONFIG_RAMFS y
+if [ "$CONFIG_HUGETLB_PAGE" = "y" ]; then
+ tristate 'HugeTLB file system support' CONFIG_HUGETLBFS
+fi
+
tristate 'ISO 9660 CDROM file system support' CONFIG_ISO9660_FS
dep_mbool ' Microsoft Joliet CDROM extensions' CONFIG_JOLIET $CONFIG_ISO9660_FS
dep_mbool ' Transparent decompression extension' CONFIG_ZISOFS $CONFIG_ISO9660_FS
@@ -72,7 +76,11 @@
bool '/proc file system support' CONFIG_PROC_FS
-dep_bool '/dev file system support (EXPERIMENTAL)' CONFIG_DEVFS_FS $CONFIG_EXPERIMENTAL
+if [ "$CONFIG_IA64_SGI_SN1" = "y" -o "$CONFIG_IA64_SGI_SN2" = "y" ] ; then
+ define_bool CONFIG_DEVFS_FS y
+else
+ dep_bool '/dev file system support (EXPERIMENTAL)' CONFIG_DEVFS_FS $CONFIG_EXPERIMENTAL
+fi
dep_bool ' Automatically mount at boot' CONFIG_DEVFS_MOUNT $CONFIG_DEVFS_FS
dep_bool ' Debug devfs' CONFIG_DEVFS_DEBUG $CONFIG_DEVFS_FS
diff -Nru a/fs/Makefile b/fs/Makefile
--- a/fs/Makefile Wed Oct 8 09:05:48 2003
+++ b/fs/Makefile Wed Oct 8 09:05:48 2003
@@ -28,6 +28,7 @@
subdir-$(CONFIG_EXT2_FS) += ext2
subdir-$(CONFIG_CRAMFS) += cramfs
subdir-$(CONFIG_RAMFS) += ramfs
+subdir-$(CONFIG_HUGETLBFS) += hugetlbfs
subdir-$(CONFIG_CODA_FS) += coda
subdir-$(CONFIG_INTERMEZZO_FS) += intermezzo
subdir-$(CONFIG_MINIX_FS) += minix
diff -Nru a/fs/inode.c b/fs/inode.c
--- a/fs/inode.c Wed Oct 8 09:05:48 2003
+++ b/fs/inode.c Wed Oct 8 09:05:48 2003
@@ -56,7 +56,7 @@
*/
static LIST_HEAD(inode_in_use);
-static LIST_HEAD(inode_unused);
+LIST_HEAD(inode_unused);
static struct list_head *inode_hashtable;
static LIST_HEAD(anon_hash_chain); /* for inodes with NULL i_sb */
diff -Nru a/include/linux/agp_backend.h b/include/linux/agp_backend.h
--- a/include/linux/agp_backend.h Wed Oct 8 09:05:48 2003
+++ b/include/linux/agp_backend.h Wed Oct 8 09:05:48 2003
@@ -55,6 +55,7 @@
INTEL_I855_PM,
INTEL_I860,
INTEL_I865_G,
+ INTEL_460GX,
VIA_GENERIC,
VIA_VP3,
VIA_MVP3,
@@ -129,6 +130,7 @@
size_t page_count;
int num_scratch_pages;
unsigned long *memory;
+ void *vmptr;
off_t pg_start;
u32 type;
u32 physical;
diff -Nru a/include/linux/fs.h b/include/linux/fs.h
--- a/include/linux/fs.h Wed Oct 8 09:05:47 2003
+++ b/include/linux/fs.h Wed Oct 8 09:05:47 2003
@@ -244,7 +244,7 @@
/* First cache line: */
struct buffer_head *b_next; /* Hash queue list */
unsigned long b_blocknr; /* block number */
- unsigned short b_size; /* block size */
+ unsigned int b_size; /* block size */
unsigned short b_list; /* List that this buffer appears */
kdev_t b_dev; /* device (B_FREE = free) */
diff -Nru a/include/linux/highmem.h b/include/linux/highmem.h
--- a/include/linux/highmem.h Wed Oct 8 09:05:48 2003
+++ b/include/linux/highmem.h Wed Oct 8 09:05:48 2003
@@ -84,7 +84,7 @@
static inline void clear_user_highpage(struct page *page, unsigned long vaddr)
{
void *addr = kmap_atomic(page, KM_USER0);
- clear_user_page(addr, vaddr);
+ clear_user_page(addr, vaddr, page);
kunmap_atomic(addr, KM_USER0);
}
@@ -116,7 +116,7 @@
vfrom = kmap_atomic(from, KM_USER0);
vto = kmap_atomic(to, KM_USER1);
- copy_user_page(vto, vfrom, vaddr);
+ copy_user_page(vto, vfrom, vaddr, to);
kunmap_atomic(vfrom, KM_USER0);
kunmap_atomic(vto, KM_USER1);
}
diff -Nru a/include/linux/sysctl.h b/include/linux/sysctl.h
--- a/include/linux/sysctl.h Wed Oct 8 09:05:47 2003
+++ b/include/linux/sysctl.h Wed Oct 8 09:05:47 2003
@@ -146,6 +146,7 @@
VM_MAX_MAP_COUNT=11, /* int: Maximum number of active map areas */
VM_MIN_READAHEAD=12, /* Min file readahead */
VM_MAX_READAHEAD=13, /* Max file readahead */
+ VM_HUGETLB_PAGES=14 /* Number of available huge pages */
};
diff -Nru a/kernel/sysctl.c b/kernel/sysctl.c
--- a/kernel/sysctl.c Wed Oct 8 09:05:47 2003
+++ b/kernel/sysctl.c Wed Oct 8 09:05:47 2003
@@ -30,6 +30,7 @@
#include <linux/init.h>
#include <linux/sysrq.h>
#include <linux/highuid.h>
+#include <linux/hugetlb.h>
#include <asm/uaccess.h>
@@ -290,6 +291,10 @@
&vm_max_readahead,sizeof(int), 0644, NULL, &proc_dointvec},
{VM_MAX_MAP_COUNT, "max_map_count",
&max_map_count, sizeof(int), 0644, NULL, &proc_dointvec},
+#ifdef CONFIG_HUGETLB_PAGE
+ {VM_HUGETLB_PAGES, "nr_hugepages", &htlbpage_max, sizeof(int), 0644, NULL,
+ &hugetlb_sysctl_handler},
+#endif
{0}
};
diff -Nru a/mm/mremap.c b/mm/mremap.c
--- a/mm/mremap.c Wed Oct 8 09:05:48 2003
+++ b/mm/mremap.c Wed Oct 8 09:05:48 2003
@@ -9,6 +9,7 @@
#include <linux/shm.h>
#include <linux/mman.h>
#include <linux/swap.h>
+#include <linux/hugetlb.h>
#include <asm/uaccess.h>
#include <asm/pgalloc.h>
@@ -272,6 +273,10 @@
vma = find_vma(current->mm, addr);
if (!vma || vma->vm_start > addr)
goto out;
+ if (is_vm_hugetlb_page(vma)) {
+ ret = -EINVAL;
+ goto out;
+ }
/* We can't remap across vm area boundaries */
if (old_len > vma->vm_end - addr)
goto out;